Draw the expanded structure of the Von Neumann Architecture or IAS computer.

Expanded Structure of Von Neumann Architecture

The expanded structure of the Von Neumann Architecture or the IAS computer is given below,



Draw the expanded structure of the Von Neumann Architecture or IAS computer.

Legends of the above given figure are given below,


  1. MBR (Memory Buffer Register): MBR is a two-way register that holds the data fetched from memory and ready for the CPU to process or the data waiting to be stored in memory.
  2. MAR (Memory Address Register): MAR specifies the address in memory of the word to be written from or read into the MBR.
  3. IR (Instruction Register): IR contains the 8-bit op-code instruction being executed.
  4. IBR (Instruction Buffer Register): IBR is employed to hold temporarily the right-hand instructions from a word in memory.
  5. PC (Program Counter): PC is an counter that contains the address of the next instruction-pair to be fetched from memory to be executed.
  6. AC and MQ (Accumulator and Multiplier Quotient): AC and MQ are employed to hold temporarily operands and results of ALU operations.

Author: Tanmay Chakrabarty

Tanmay Chakrabarty is a former CSE student, currently working as a Senior Software Engineer with 5+ years of experience in the field of Web Application development in PHP+MySQL platform with strong skills in Javascript, JQuery, JQuery UI and CSS. He tries to write notes every week but fails due to heavy loads of duty.

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